SDRAM: The Speedmeister Of Digital Systems

by Reggie Huff

DRAM has always been a cheap form of memory. Should be. It forgets what it was told to remember in 50 or 60 milliseconds. So, in order to reap the dramatic cost-per-bit savings, one merely needs to check with each memory cell about 20 times per second to ask it what it was supposed to remember, and then remind it to remember that!

Analog systems, once the premier platform of electronic design, have been driven to near extinction by the "asynchrocidal" digital revolution. Revolutionist leaders have implicitly insisted that the greater good would be served when every circuit would finally conform to the tick of a single clock. Memory chips (bless their defiant souls) have traditionally retained the freedom and independence that asynchronicity affords. No longer. Today's frantic pace and ever-expanding "to do" list has finally driven even the forgetful DRAM into fully synchronized operation.

Without the use of geometric reductions, refined lithography, or breakthroughs in materials science, synchronous DRAM (SDRAM) provides unprecedented silicon data transfer rates. In fact, SDRAM is capable of supporting today's 100-MHz microprocessors without cache, without multichip expense, and without the speed-curbing frustration of the dreaded wait state. Synchronous DRAM blows the lid off system speeds by integrating multichip memory management strategies into blazing monolithic solutions.

SDRAM functionality is principally distinguished by four features:

Synchronous Operation: The system clock gates all SDRAM operations. (Conventional DRAM has no clock input.)

Cell Banks: Internally, memory cells are divided into independently accessed "cell banks," which may be treated as if they were separate memory chips. This makes it possible to address a location in one bank while simultaneously reading the data requested during a previous cycle from another bank. While the first read cycle is as long as a typical DRAM's, subsequent cycles conduct the address input and data output delays concurrently, resulting in increased data transfer rates. This method is called pipelining.

Burst Mode: This rapid data- transfer technique is accomplished through the use of an Internal Column Address Generator. Once the column address for the first memory location is set, subsequent addresses are automatically generated internally. Either sequential (for Motorola CPUs) or interleaved (for Intel CPUs) address sequences may be programmed for automatic generation. Burst mode may be applied for data transfers into memory (burst write) or out of memory (burst read). The number of words to be transferred with each "burst" can also be specified.

Command (Mode) Storage Registers: These internal registers are loaded with system configuration command codes upon power up which define column-address strobe latency, the burst type and burst length desired, addressing mode, test mode, and various supplier-specific options to optimize the SDRAM performance in a wide variety of applications.

If doing more things faster with fewer chips is our aspiration, then SDRAM will be an architecture which, along with process technology advancements, will pioneer the frontiers of throughput right into the next revolution.

"SDRAM: The Speedmeister Of Digital Systems" first appeared in Electronics Buyers News, Issue 987, January 2, 1996

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