ABCs of PLDs

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The ABCs of PLDs

In the spring of 1981 I made a horrible, life altering, mistake.

With chimerical ambition, I cut my hair off, exchanged my sandals for wing tips, my T-shirts for ties, the beaches of Santa Barbara for the Silicon Valley rush hour traffic and... I left the university to become an applications engineer at Fairchild Camera & Instrument. To my chagrin, I was soon to discover that Fairchild made neither cameras nor instruments. I was almost immediately rewarded, however, with
• a professional image (to uphold)
• a personal & private cubicle
• a substantial and hefty steel desk
• a mint-condition Fairchild Data Book
• a Styrofoam coffee cup
• absolutely unlimited telephone privileges

Life has never been quite the same.

Back then, immediately following the "Good Ole Days," the Texas Instruments 74LSXX series data book was THE digital designers bible. It contained data sheets on dual-input-AND gates, OR gates, NOR gates (four to a chip). You could get latches, flip-flops, and hex-inverters (six to a chip). A logical smorgasbord to feast upon. Back then the process of designing digital systems involved wiring the output of one gate to the input of others. The others were inevitably on another chip and in another package, meaning that each and every one needed to be located from stock, installed on the board, and literally connected to any preceding (and subsequent) stages of logic. The boards got big pretty fast, the interconnects rapidly became clumsy and congested, and "de-bugging" was, by far, the biggest part of the project.

If you've ever been involved in any substantial building project with Tinker Toys or Legos, you've immediately appreciated the notion of some kind of computer automation that lets you click-and-choose the parts, snap-and-build on-screen, and then somehow spits out the real-world construction right in your living room. At the time, IC design engineers enjoyed that level of luxury with their pre-historic CAD for silicon systems. However, board-level system designers had to resort to building their "toys" with the simple 2-, 4-, 6-, or 8-gate-per-DIP components they had in the TTL "toy box."

PLD is an acronym for Programmable Logic Device. Such a product might, just as well, have been named Programmable Logic Chip (PLC) or Programmable Logic IC (PLIC) or Programmable Logic Part (PLP). It wasn't. Somebody picked the word device. The logic part of the name refers to logic gates-the same ones we used to build with from the 74LSXX bible. The magic all lies in the programmable part of the name.

Programmability means that the outputs of one gate may be connected to the inputs of other gates RIGHT ON THE CHIP! So instead of all of those parts sitting in inventory and getting inter-connected through wires around a board, they might all simply exist on a single sliver of silicon. The interconnects may be configured on a chip-by-chip basis. What a fantastic advance in the world of digital Tinker Toys!

The Conceptual PLD diagram below shows but a small corner of even the simplest of PLDs. The idea is that by opening or closing the various switches between the vertical and horizontal conductors, one can configure connections between any of the chip-input signals (a,b, c, etc.) and the AND-gate inputs. In this way system designs formerly requiring a multitude of chips and interconnects strewn over a PC board can be implemented within a single chip and IC package.

Configurable Logic Array

The extreme advantages of the PLD included:
• TIME TO MARKET
• Huge Inventory Reductions
• TIME TO MARKET
• Increased System Reliability
• TIME TO MARKET
• Reduced Power Requirements
• TIME TO MARKET
• Substantial Board Space Reductions
• TIME TO MARKET
• Elimination of most of the de-bug time
And, I almost forgot, TIME TO MARKET!

Fuse Method
One way to implement these "switches" on the silicon is to use top-layer metal to form conductive bridges between each and every vertical and horizontal signal pathway in the "array." Clearly, with this configuration the device would be useless. This is the condition in which manufacturers ship and customers receive them.

Fuse Method Configurable (OTP) Logic Array

These PLDs are then programmed by placing them in a Programmer machine which sends too much current through every connection that is to be eliminated. When this happens, those metal bridges get warm, and then hot, until finally, they vaporize (just like those see-through fuses at Grandma's house). Those connections are thus permanently disconnected, leaving the others, which were not vaporized, to establish the intended signal connection and, thereby, the logic configuration.

Since this "blowing the fuse" process is irreversible, each device can only be programmed once and is therefore said to be a One-Time-Programmable (OTP) PLD.

Transistor Method
Since transistors are simply regions in the silicon that can be transformed from conductors to insulators and visa versa (just like a switch), they have been used in place of those conceptual switches (shown above) as an alternate means of configuring the logic. Since transistors can be repeatedly turned ON and OFF without damage, PLDs using this technique are said to be reconfigurable.

Transistor Method
Re-Configurable Logic PAL Array

Volatile/Non-volatile Configuration
Control of these transistors being turned ON or OFF (set) can be implemented in different ways. Volatile (SRAM-type) transistors lose their "setting" when power is turned off and therefore need to be reset each time system power comes back on. Non-volatile (EPROM, EEPROM, FLASH) transistors retain their "setting" even when power is turned off. PLDs based on these technologies can be configured once and forever after maintain their logic function. Yet because they are flexibly re-programmable, the logic function can be changed repeatedly-though this rarely happens except during system development.

Logic Array Types and Elements
PAL is an acronym for Programmable Array Logic. PALs constitute a popular family of products exhibiting a variety of features and gate counts. They are distinguished by a feature of their logic array which is that, while the inputs to the AND-gates are user-configurable, the connections to the OR-gates is hard wired and inalterable (as in all of the diagrams shown above).

PLA is an acronym for Programmable Logic Array. PLAs also come in an ever expanding family of devices characterized by a multitude of features and gate counts. Unlike the PAL family of products, PLAs exhibit the additional flexibility of allowing the user to freely configure the inputs controlling the OR-gates in addition to those controlling the AND-gates (as shown below).

PLA Array

FPGA is an acronym for Field Programmable Gate Array. FPGAs are typically far denser and more complex than PALs or PLAs. FPGAs are conceptually different in that they are arranged as a collection of cells that contain various higher-level-logic functions. These FPGA cells are then interconnected through the configuration of on-chip routing buses (as shown below).

FPGA Array

There is much, much more to be said about the PLD clan and each of its families. If you are interested in exploring this topic further, please let me know and we'll dedicate some future columns.

"The ABCs of PLDs" first appeared on EBNONLINE.COM on October 25, 1999.