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How Extended Data Out DRAMs Speed Memory Access

In the accelerating quest for ever faster data access, memory chip manufacturers are both striving to refine manufacturing technology and pressing their design engineers for innovative circuit tricks. In this first column I'll explain one of these design innovations popularized by the EDO DRAM, originated by Micron Technology.

First, some memory chip basics. System memory is typically comprised of either a few or a bunch of individually selectable memory chips. Within each chip, individual words of information may be stored at, or read from, specific "addressable" locations containing one or more "bits." The number of bits that are stored at any one location is known as the "width" of the memory array. Memory chips are available in a variety of bit widths from one to 64. These "addressable" locations are portrayed as home mailboxes having eight bits of storage. Specific mailboxes (memory locations) are identified by the street (row address) and the house number (column address)

In operation, the system provides both a row and a column "address" to the chip to identify a memory location. In some memory types, these row and column addresses are decoded from a single group of bits. In other types, such as EDO DRAM, Row Address Strobe (RAS), and Column Address Strobe (CAS), signals are used to "clock" separate row and column addresses into the device.

Whenever the address changes, there is a slight time delay called "pre-charge" time. This is the time it takes for electrons to flow along the addressed paths, to charge up the set of devices which will route the information contained in the newly addressed location to the data pins of the chip.

Page Mode, a common feature in larger memory devices, uses "Postman Techniques" to reduce delays. A "page" is simply the set of memory locations that all fall on the same row. In Page Mode, only column addresses are changed between subsequent locations. This provides efficiencies similar to those of a "Postman" who proceeds from house to house along a street instead of randomly pulling letters out of the mail bag and driving to whatever address is on the envelope (the overnight delivery method). In Page Mode, time is saved since sequential memory accesses don't require row address changes.

EDO is an acronym for Extended Data Out, and it names a very clever feature. "Extended Data Out" means that data remains available on the output pins for an extended period of time. It is implemented by designing a D-type flip-flop into into the output buffer of an otherwise standard DRAM. Hence, the data pins of an EDO DRAM are marked "DQ": "Dn" is standard nomenclature for memory data pins; Q is the standard marking for the data out pins of flip-flops.

EDO reduces effective memory access times by latching and holding data on the DQ output pins while, within the chip, the next location to be accessed is getting set up. It allows for overlapping the read cycle of one location with the pre-charge time of the subsequent location. Clearly, this technique will continue to provide an advantage to DRAM speeds as manufacturing technology continually advances standard DRAM speeds. By combining Page Mode operations with EDO, effective data access speeds may be doubled or even quadrupled.

While EDO DRAMs offer attractive speed increases over traditional DRAMs, the use of EDO requires engineering changes in systems designed for traditional DRAMs. EDO DRAMs are being manufactured by an increasing number of suppliers, and are finding their way into an expanding variety of consumer products.

"How Extended Data Out DRAMs Speed Memory Access" first appeared in Electronics Buyers News, Issue 960, June 19, 1995