by Reggie Huff

Most conventional memory types reliably remember their stuff as long as you don't destroy them. Seems like they should since remembering stuff is their sole purpose in the world.

From old-fashioned vinyl records through the familiar audio/video tapes, to the floppy, hard, and compact discs of today, the information stored on them is retained whether they are being used or mothballed.

Most semiconductor memories are like that. ROM, PROM, EPROM, EEPROM, and FLASH are pretty good about maintaining their data integrity under any conditions short of extreme abuse. Each of these memory devices fall into a family called Non-Volatile memory.

This Non-Volatile quality distinguishes them (obviously) from the Volatile memory types. Volatile memories all share one very un-endearing characteristic, which is that each and every time that there is a loss of electrical power...they instantly and completely forget everything they were supposed to remember.

If you've ever suffered the exasperation of losing hours of work because your computer shut off unexpectedly...

If you've ever gotten your car back from the mechanic to find your programmed radio stations all forgotten...

If you've ever discovered that the speed-dial numbers you'd carefully put into your phone were lost upon changing the battery...

...then you've experienced the heartbreak of volatile memory. When the power goes away ­ even briefly ­ so does the memory.

The 'S' in SRAM stands for Static, meaning that it retains any information which is stored in it, as long as power is maintained without any outside help. The data just sits there, calmly awaiting retrieval by the system command. Upon receiving an order to over-write the data or to provide some data being retained, the SRAM is very fast to respond. That's one of it's endearing qualities.

The 'D' in DRAM stands for Dynamic, meaning that the storage medium itself is constantly changing (forgetting). DRAM is one of the cheapest forms of memory. Certainly it should be, because it completely forgets what it was told to remember in 5 or 6 hundredths of a second. Every time.

In order to reap the dramatic cost-per-bit savings which DRAM offers, we need to visit each and every bit many times each second, ask it what it was supposed to remember, and then remind it to remember what it was remembering before it forgets altogether. This reminding process is called "refreshing" the memory, and we have devised a wide variety of sophisticated refresh circuits which do nothing but cruise through the vast DRAM memory array polling each bit for its content before it fully forgets, and re-telling the memory what it's supposed to remember.

A Byte of Barrels
A good analogy would be a "byte" of eight rusty metal barrels standing side by side somewhere in the forest. The idea is that I will use them to encode a message for you to retrieve at some later time when you come upon them while walking in the forest. Here's the code: for each barrel, if it is filled with water above the two-thirds mark it's a "1." If it is less than one-third filled with water it is a "0." This is a pretty easy plan except for one thing-old, rusty barrels tend to leak.

That's not a problem for the barrels in which I intend to store the 0s, because if they leak down to empty...well, they're still 0s. It is, however, a problem for the barrels in which I intend to store the 1s. I'll be sure to fill them up to the top, but if you don't get there before they leak down past the two-thirds mark, well, you'll never know a 1 was ever there.

Enter the Ladle Guy. The Ladle Guy carries a ladle as he treks from "barrel byte" to "barrel byte" throughout the forest. His job is to get there before the barrels leak down past the two-thirds mark. Upon his arrival, he checks each barrel in turn, and if it's filled above the two-thirds mark, he tops it off. If not, he leaves it alone. As long as he "refreshes" the filled barrels in timely way, he doesn't have to know what they were supposed to be storing; he just checks and refreshes as appropriate.

The DRAM storage mechanism is merely a tiny capacitor, and so, when it is set to a 1 it is filled with charge. That charge immediately begins leaking away when the charger departs. The refresh circuits simply restore a full charge to those bits that were remembering to be 1s. The disadvantage of this type of ephemeral memory is tolerated in trade for the advantage of its very tiny size and simple structure. Having a memory cell so small allows us to put more of them on any given device, and that's why DRAM leads the memory clan in terms of providing the most bits per chip.

Upon occasion, designers have moved that Refresh Circuit from the system board directly onto the DRAM chip itself. When this is done, from the outside, it would appear that the memory is behaving statically, or that is does not require any dynamic refresh. Of course this is illusionary, since each memory cell is being constantly refreshed on the chip. When the refresh circuit is integrated into the DRAM chip itself, the device is called a Pseudo Static DRAM.

At this point, the alert reader following the acronym progression might be wondering if SDRAM is some kind of Static/Dynamic RAM. It is not. In the case of SDRAM, the "S" stands for Synchronous and designates a relatively recent innovation in IC memory management techniques wherein we force the IC-memory circuits to march in step with the system clock instead of allowing them the asynchronous freedom to respond at their own pace, on their own schedule.

This notion brings us to the brink of exploring the many memory management techniques evolving today, including Page Modes, EDO DRAM, Pipelining, Burst-modes, and Interleaving.

"DRAM and SRAM: A Very Volatile Clan" first appeared on EBNONLINE.COM on November 9, 1999.

© Copyright 1999, 2000, 2001 Huff Communications. All Rights Reserved.